Device density and circuit functionality are the twin touchstones of the semiconductor industry. The combination of these two criteria are driving the industry to create each new generation of products which are smaller, faster, more functional and less expensive than the prior generation. Unfortunately, these two goals are in opposition to a third, equally important measure, manufacturing testability. No product, however small, fast or functional, can be marketed if the product can not be expected to operate as designed. As products get smaller, faster, and more functional, the number of parameters to be tested increases. And, each parameter becomes more inconvenient to test.
One approach to testing clocked circuits or portions of clocked circuits is by creating scan chains. These circuits may be difficult to test because they are difficult to isolate either functionally or physically from other circuits. A circuit incorporating this method is sometimes referred to as level-sensitive scan design ("LSSD"). In an LSSD circuit, the input 0f each critical latch (a bit cell, the receiver of the output of some block of combinatorial logic, etc.) receives two inputs. The first input is the normal functional data as required by the operation of the latch. The second input is the output from some other latch which is located nearby. A certain number of these critical latches are combined in this way to create a chain. The input to the first latch and the output of the last latch in the chain are connected to the circuit's output pins. During testing, each latch in the LSSD circuit is configured to receive the data output from the nearby latch and particular test data is directly loaded into each of the latches. The circuit is then configured to operate normally and the machine state advanced one or more clock cycles. Finally, the LSSD circuit is configured into the test mode and the data stored in the chains latches is output to verify the proper operation of the data.
The LSSD method results in certain complications which may be worse than they problem they are intended to solve. For instance, pass gate multiplexers require that only one control signal be asserted ("one hot") at a time. Otherwise, the multiplexer will connect two different inputs to the same output node. If the two inputs are different voltage levels, then the multiplexer will cause an electrical short-circuit. Normally, the logic generating the multiplexer's control signals guarantees that only one input signal will ever be asserted, avoiding the electrical short-circuit. However, in an LSSD circuit, it is impossible to guarantee that a certain combination of data will never be input to a particular set of latches during scan in or scan out. Therefore, if the inputs to a pass gate multiplexer are latched and are part of an LSSD chain, then it is impossible to guarantee that the multiplexer will not cause an electrical short-circuit.